1. Field of the Invention
The invention relates generally to the design of integrated circuits, and more particularly, to logic optimization and clock latency scheduling during integrated circuit design.
2. Description of the Related Art
Integrated circuit designs often are quite unbalanced with respect to the timing criticality of their logic paths. That is, optimization of combinational logic paths in a circuit design may be limited by critical paths even though there may be room for additional optimization of sequential paths in the same design. As a result traditional synthesis techniques may overdesign combinational logic paths to speed up gates through resizing, for example, which may incur a significant cost in area, even when there is slack in sequential paths in the design.
Sequential optimization techniques have been researched for many years and there are a number of efficient approaches available that are applicable to practical designs. Sequential synthesis methods of practical interest are retiming (see, C. Leiserson and J. Saxe, “Optimizing synchronous systems,” Journal of VLSI and Computer Systems, vol. 1, pp. 41 67, January 1983; C. Leiserson and J. Saxe, “Retiming synchronous circuitry,” Algorithmica, vol. 6, pp. 5 35, 1991) and clock latency scheduling (see, J. P. Fishburn, “Clock skew optimization,” IEEE Transactions on Computers, vol. 39, pp. 945 951, July 1990). In both cases, the goal is to balance the path delays between registers and thus to maximize the performance of the design without changing its input/output behavior.
Retiming involves structural transformation that moves the registers in a circuit without changing the positions of the combinational gates. Typical retiming does not address the problem of overdesigned combinational logic paths since commonly used formulations assume a fixed gate timing. For a given set of gate delays retiming ordinarily involves either minimizing the number of registers, maximizing performance, or targeting some combination of the two objectives. Retiming interleaved with synthesis (see, S. Malik, E. M. Sentovich, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Retiming and resynthesis: Optimizing sequential networks with combinational techniques,” IEEE Transactions on Computer-Aided Design, vol. 10, pp. 74-84, January 1991) can distribute slacks in a limited manner. However, it still applies hard paths partitioning and thus may not predictably balance all slacks.
In contrast to retiming, clock latency scheduling preserves the circuit structure, but applies tuned delays to the register clocks—thus virtually moving them in time. Recently, clock latency scheduling has been adopted in some design flows as a post-layout optimization technique to reduce the cycle time (see, I. S. Kourtev and E. G. Friedman, Timing Optimization through Clock Skew Scheduling. Boston, Dortrecht, London: Kluwer Academic Publisher, 2000) and the number of close-to-critical paths (see, C. Albrecht, B. Korte, J. Schietke, and J. Vygen, “Cycle time and slack optimization for VLSI chips,” in Digest of Technical Papers of the IEEE International Conference on Computer-Aided Design, pp. 232-238, November 1999; S. Held, B. Korte, J. Maβberg, M. Ringe, and J. Vygen, “Clock scheduling and clocktree construction for high-performance ASICs,” in Digest of Technical Papers of the IEEE/ACM International Conference on Computer-Aided Design, (San Jose, Calif.), pp. 232-239, November 2003). Clock latency scheduling can be viewed as a relaxed form of retiming which is computationally less complex.
Thus, there has been a need to better utilize sequential optimization techniques to further optimize combinational logic synthesis. The present invention meets this need.